The present invention relates to a digital/analog mixed type semiconductor integrated circuit wherein a digital circuit and analog circuit are formed on the same semiconductor substrate. In particular, the present invention relates to a digital/analog mixed type semiconductor integrated circuit such as a CMOS (complementary metal oxide semiconductor)-type solid-state image sensing device or the like which incorporates a digital signal processing circuit and an A/D (Analog/Digital) converter and handles weak analog signals.
With a more highly integrated semiconductor circuit, the system-on-chip method, in which one system is formed on the same substrate, is being used more widely. A digital/analog mixed type semiconductor integrated circuit is also being used wherein a digital circuit and an analog circuit often provided on separate chips conventionally are formed on the same substrate.
In such a digital/analog mixed type semiconductor integrated circuit, there is a problem that digital noises generated upon an operation of the digital circuit adversely affect an operation of the analog circuit via a power source, ground, substrate or the like.
This occurs primarily for the following reasons. That is, CMOS circuits are generally used for a digital circuit for higher integration and lower power consumption. In this CMOS circuit, a charge or discharge current charging or discharging a load capacitance when an output is inversed or a through-current flowing from a power source to a ground within an element flows only for a very short period. Therefore, a large power source current flows within the digital circuit immediately after a clock level changes, and thereafter almost no current flows until the clock level changes.
Due to such an abrupt change of the power source current, the power source voltage changes or the capacitance of a junction formed between a diffusion layer of a transistor and a semiconductor substrate is charged or discharged depending on the transistor operation. Then, this change adversely affects an operation of the analog circuit via the semiconductor substrate and produces noises.
FIG. 6 is a block diagram of a conventional A/D converter incorporated CMOS-type solid-state image sensing device which is typical as a digital/analog mixed type semiconductor integrated circuit. In the figure, a timing generator 1 generates various sensor drive pulses for driving a sensor 2 and generates a basic clock ADCK for driving an A/D converter 3 at the same time. In a case of such an integrated circuit, as described above, a noise component generated by an operation of the A/D converter 3 is often mixed in a weak analog signal component of the sensor 2.
As a countermeasure against this case, besides methods of improving a design of a wiring pattern, pin layout or the like, for example, there is a method of relatively shifting a clock signal phase for operating the analog circuit and that of the digital circuit. When the clock phases are to be shifted, however, it is very difficult to predict an optimum clock phase difference before designing since a shift amount of the clock phases is changed in practice by a wiring resistance, stray capacitance or the like within a device.
Accordingly, to solve such problems, such a semiconductor integrated circuit device as disclosed in Japanese Patent Laid-Open Publication No. 6-283999 has been proposed. In this semiconductor integrated circuit device, clock phase difference generating circuits generating several kinds of clock phase differences are prepared in advance. Then, in an experimental stage, a sine-wave generator and a spectrum analyzer are connected thereto and a clock phase difference generating circuit for generating a clock phase difference which produces least noises in the analog circuit is selected. In a mass production stage, the sine-wave generator and the spectrum analyzer are removed and only one mask is changed out of the mask configuration in the experimental stage. Thus, a wiring pattern is fixed so that only the above selected clock phase difference generating circuit is activated.
In the conventional semiconductor integrated circuit device, however, there are problems described below. That is, once a clock phase difference generating circuit is selected, the wiring pattern is fixed so that only this clock phase difference generating circuit is activated in the manufacturing stage. Therefore, the clock phase difference is not changed thereafter. However, in a process of manufacturing an integrated circuit, it is natural that variation in transistor characteristics, resistance or the like occurs during manufacturing. Therefore, that clock phase difference generating circuits which are the same on design do not always generate a constant clock phase difference. Rather, the same clock phase difference is rarely generated in practice.
Therefore, in the above-described semiconductor integrated circuit device, a clock phase difference generating circuit producing the least noise components is not always selected.